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In MIPS, cause register is responsible for telling CPU which interrupt is happening. CPU read the IP bits in cause register and dispatch interrupt to interrupt service routine.
One question: who is responsible for clear IP bits in cause register? That is interrupt handler. Interrupt handler must clear the corresponding IP bit in cause register, othewise [...]
Caution: This article is out-dated. You can find the new how to in rockbox's wiki.
This article describes how to run rockbox on vx747 and vx747+.
1. Download rockbox from daily archive or svn. I use the svn version 19703.
2. build the toolchain. You can build the toolchain from ingenic or use the script in rockbox to [...]
1. u-boot and linux kernel can boot from mmc image
2. Because twl4030 emulation is not complete, mmc device can not be found in linux kernel.
Next step:
1. twl4030 emulation. Big effort is needed.
2. dss/dma emulation
3. usb
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