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Before reading this article, please please visit the following website and help this little girl. She is the daughter of panjet, the core member of this project. Without him, this project can not even happen.
http://yifanfund.com (English)
在阅读这篇文章前, 我恳请您花一点时间来帮助panjet的女儿怡帆. Panjet是这个项目的核心成员.如果没有他的参与,这个项目不可能成功地port linux到vx747上面. 赠人玫瑰,手留余香.  您的爱心一定能让小怡帆度过目前的困难.
http://help-yifan.org (中文)

Hi guys, a good news for you who are interested in running linux [...]

Feb 24th, 2009 | Filed under JZ, kernel

In MIPS, cause register is responsible for telling CPU which interrupt is happening. CPU read the IP bits in cause register and dispatch interrupt to interrupt service routine.
One question: who is responsible for clear IP bits in cause register? That is interrupt handler. Interrupt handler must clear the corresponding IP bit in cause register, othewise [...]

Jan 16th, 2009 | Filed under JZ, emulation